Landmark Arm Morello CPU now available for testing
New CHERI instruction set allegedly eliminates almost all memory safety issues.
British companies can now apply to test the landmark Arm Morello system-on-a-chip -- an architecture developed as part of a major public-private project to improve hardware security. The pilot will include six months’ access, guidance and potential funding from the consortium involved, Digital Security by Design (DSbD).
UK companies have until 8 September to apply to DSbD’s Technology Access Programme (TAP), which will give successful applicants access to a Morello board, featuring an experimental Armv8.2-A CPU.
That has been adapted from Arm's Neoverse N1 processor and uses new hardware mechanisms to access memory intended to mitigate memory vulnerability issues. (Arm notes that the architecture "goes beyond memory safety [and can be a] building block for the finer-grained compartmentalization of software..."
All successful companies will get access to the Arm Morello board for six months, technical support from DSbD, and access to Digital Catapult’s 5G and IoT labs, while companies with under 250 employees will also get a £15,000 grant and one-to-one sessions. (Academic institutions or organisations outside the UK can also apply for a Morello board, without the additional UK government support.)
“Companies interested in participating will need a strong engineering team and a company culture invested in exploring, experimenting and inventing using new technologies. They will also need to be able to evaluate C and C++ on new architectures, in the context of performance and improving security,” said Katy Ho, head of innovation practice at Digital Catapult, in an email to The Stack.
“With a strong focus on security, participants ideally work with sectors that have safety critical systems e.g. aerospace, autonomous systems, healthcare, supply chain, telecommunications, transportation, and utilities.”
What is the Arm Morello SOC?
Arm’s Morello programme is designed to improve CPU and code security by mitigating memory safety vulnerabilities – limiting how code in some parts of memory can access code in other parts.
"Morello implements CHERI: Capability Hardware Enhanced RISC Instructions, (and winner of our Tortured Acronym of the Month award) on a system-on-chip, which is provided on the Morello board.
CHERI is a joint project between Cambridge University and SRI International (formerly the Stanford Research Institute), supported by DARPA and, since 2019 when Arm became involved, UK Research and Innovation – along with EPSRC, ERC and Google. Cambridge University describes CHERI as a “hybrid capability architecture” capable of blending different architectural capabilities – meaning it can run existing software which hasn’t been optimised for the instruction set.
“The purposes of Morello are to enable industrial evaluation of the CHERI hardware and software ideas, to gather evidence for adoption, and to support further related research and development. This will be enabled by applying CHERI to a widely deployed, real-world architecture via a high-end mature processor design, and a mature software ecosystem,” said a guide on Morello from Cambridge University.
According to Ho, CHERI can eliminate most memory safety issues in C and C++.
Who’s using Morello and CHERI already?
The Morello board has been available since early 2022, with 10 companies initially given access to the system, according to Ho: “Amongst the first cohort of the TAP were Inventia, who will develop a server backend for SIM-based localisation services for mobile operators, and Riskoa, who provide digital solutions for water management, and will be porting existing software for water monitoring sensors to the Morello board.
“Prior to TAP and hardware availability, a number of companies experimented with a Fixed Virtualisation Platform (FVP). An example is Pytilia, a software company based out of Belfast, Northern Ireland,” she added. “Pytilia applied the CHERI memory model to improve performance using DSbD hardware-based capabilities, instead of classic memory pointers requiring manual checks.”
The hope of DSbD and Digital Catapult is for TAP participants to produce “compelling examples of security and performance enhancements” using Morello and CHERI, and find new use-cases for the technology.
“Once all companies have successfully completed the Technology Access Programme, Digital Catapult will be hosting a showcase event in March 2023 to share the outcome of their experiments,” Ho told The Stack.
How long? Not long…
If this sounds of interest, applications are open until 8 September.
